PATMOS 2004 - PDF Preprint Papers

PATMOS 2004 International Workshop on Power and Timing Modeling

Teaser Browsing | Click Here

Title Browsing | Click Here

Wall of Fame | Most Viewed PATMOS-2004 Paper

click to vote

PATMOS
2004
Springer

195views Modeling and Simulation» more PATMOS 2004»

Optimal Logarithmic Representation in Terms of SNR Behavior

14 years 5 months ago

Download www.andrew.cmu.edu

This paper investigates the Signal-to-Noise Ratio (SNR) performance of the Logarithmic Number System (LNS) representation against the SNR performance of the ﬁxed-point representa...

Panagiotis D. Vouzis, Vassilis Paliouras

claim paper

Read More »

Disclaimer and Copyright Notice

Sciweavers respects the rights of all copyright holders and in this regard, authors are only allowed to share a link to their preprint paper on their own website. Every contribution is associated with a desciptive image. It is the sole responsibility of the authors to ensure that their posted image is not copyright infringing. This service is compliant with IEEE copyright.

Id	Views	Title	Status

1	195	Optimal Logarithmic Representation in Terms of SNR Behavior	claim
2	156	Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell	claim
3	149	A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip Buses	claim
4	138	Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic	claim
5	134	An Efficient Low-Degree RMST Algorithm for VLSI/ULSI Physical Design	claim
6	133	Sleepy Stack Reduction of Leakage Power	claim
7	122	Low Latency Synchronization Through Speculation	claim
8	117	Modular Construction and Power Modelling of Dynamic Memory Managers for Embedded Systems	claim
9	114	SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic Level	claim
10	112	Leakage Reduction at the Architectural Level and Its Application to 16 Bit Multiplier Architectures	claim
11	110	The Certainty of Uncertainty: Randomness in Nanometer Design	claim
12	109	A Multi-level Validation Methodology for Wireless Network Applications	claim
13	104	Power Aware Dividers in FPGA	claim
14	100	Application Analysis with Integrated Identification of Complex Instructions for Configurable Processors	claim
15	99	Leakage Power Analysis and Comparison of Deep Submicron Logic Gates	claim
16	87	Run-Time Software Monitor of the Power Consumption of Wireless Network Interface Cards	claim
17	84	Physical Extension of the Logical Effort Model	claim
18	75	Signal Sampling Based Transition Modeling for Digital Gates Characterization	claim

Sciweavers

Explore & Download

Productivity Tools

Document Tools

Image Tools

Sciweavers