85 search results - page 15 / 17 » A low overhead hardware technique for software integrity and... |
CODES
2006
IEEE
14 years 1 months ago
2006
IEEE
Design of System-on-Chip (SoC) with regular mesh based Network-on-Chip (NoC) consists of mapping processing cores to routers, and routing of the traffic traces on the topology suc...
IOLTS
2003
IEEE
14 years 1 months ago
2003
IEEE
Fault tolerant design is a technique emerging in Integrated Circuits (IC’s) to deal with the increasing error susceptibility (Soft Errors, or Single Event Upsets, SEU) caused by...
ICS
1999
Tsinghua U.
14 years 18 hour ago
1999
Tsinghua U.
Hydra is a chip multiprocessor (CMP) with integrated support for thread-level speculation. Thread-level speculation provides a way to parallelize sequential programs without the n...
EUROGRAPHICS
2010
Eurographics
14 years 4 months ago
2010
Eurographics
Hierarchical culling is a key acceleration technique used to efficiently handle massive models for ray tracing, collision detection, etc. To support such hierarchical culling, bo...
DAC
2002
ACM
14 years 8 months ago
2002
ACM
Profiling an application executing on a microprocessor is part of the solution to numerous software and hardware optimization and design automation problems. Most current profilin...