Sciweavers

12 search results - page 3 / 3
» A massively scaleable decoder architecture for low-density p...
Sort
View
ASAP
2006
IEEE
147views Hardware» more  ASAP 2006»
13 years 9 months ago
Reconfigurable Shuffle Network Design in LDPC Decoders
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...
Jun Tang, Tejas Bhatt, Vishwas Sundaramurthy
MSS
2007
IEEE
82views Hardware» more  MSS 2007»
14 years 1 months ago
Tornado Codes for MAID Archival Storage
This paper examines the application of Tornado Codes, a class of low density parity check (LDPC) erasure codes, to archival storage systems based on massive arrays of idle disks (...
Matthew Woitaszek, Henry M. Tufo