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ICCAD
2007
IEEE
87views Hardware» more  ICCAD 2007»
14 years 5 months ago
Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design
—Register allocation, in high-level synthesis and ASIP design, is the process of determining the number of registers to include in the resulting circuit or processor. The goal is...
Philip Brisk, Ajay K. Verma, Paolo Ienne
RSA
2008
123views more  RSA 2008»
13 years 8 months ago
Generating unlabeled connected cubic planar graphs uniformly at random
We present an expected polynomial time algorithm to generate an unlabeled connected cubic planar graph uniformly at random. We first consider rooted connected cubic planar graphs, ...
Manuel Bodirsky, Clemens Gröpl, Mihyun Kang
CC
2007
Springer
129views System Software» more  CC 2007»
14 years 3 months ago
Extended Linear Scan: An Alternate Foundation for Global Register Allocation
In this paper, we extend past work on Linear Scan register allocation, and propose two Extended Linear Scan (ELS) algorithms that retain the compiletime efficiency of past Linear ...
Vivek Sarkar, Rajkishore Barik
WWW
2009
ACM
14 years 9 months ago
Graffiti: node labeling in heterogeneous networks
We introduce a multi-label classification model and algorithm for labeling heterogeneous networks, where nodes belong to different types and different types have different sets of...
Ralitsa Angelova, Gjergji Kasneci, Fabian M. Sucha...
FOCS
2007
IEEE
14 years 3 months ago
Can you beat treewidth?
: It is well-known that constraint satisfaction problems (CSP) over an unbounded domain can be solved in time nO(k) if the treewidth of the primal graph of the instance is at most ...
Dániel Marx