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» A memory system design framework: creating smart memories
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VMCAI
2009
Springer
14 years 2 months ago
A Scalable Memory Model for Low-Level Code
Abstract. Because of its critical importance underlying all other software, lowlevel system software is among the most important targets for formal verification. Low-level systems...
Zvonimir Rakamaric, Alan J. Hu
ISLPED
2009
ACM
211views Hardware» more  ISLPED 2009»
14 years 2 months ago
PPT: joint performance/power/thermal management of DRAM memory for multi-core systems
With the popularity of multi-core architecture, to sustain the memory demands from different cores, the memory system is expected to grow significantly in both speed and capacit...
Chung-Hsiang Lin, Chia-Lin Yang, Ku-Jei King
ASPLOS
2010
ACM
14 years 2 months ago
Specifying and dynamically verifying address translation-aware memory consistency
Computer systems with virtual memory are susceptible to design bugs and runtime faults in their address translation (AT) systems. Detecting bugs and faults requires a clear speci...
Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. So...
VLSID
2008
IEEE
138views VLSI» more  VLSID 2008»
14 years 8 months ago
Memory Architecture Exploration Framework for Cache Based Embedded SOC
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
CODES
2000
IEEE
14 years 3 days ago
Co-design of interleaved memory systems
Memory interleaving is a cost-efficient approach to increase bandwidth. Improving data access locality and reducing memory access conflicts are two important aspects to achieve hi...
Hua Lin, Wayne Wolf