Sciweavers

3431 search results - page 143 / 687
» A new instructional operating system
Sort
View
ISVLSI
2007
IEEE
131views VLSI» more  ISVLSI 2007»
14 years 4 months ago
Improving the Quality of Bounded Model Checking by Means of Coverage Estimation
Formal verification has become an important step in circuit and system design. A prominent technique is Bounded Model Checking (BMC) which is widely used in industry. In BMC it i...
Ulrich Kühne, Daniel Große, Rolf Drechs...
DDECS
2009
IEEE
146views Hardware» more  DDECS 2009»
14 years 2 months ago
Enhanced LEON3 core for superscalar processing
Low power consumption and high-performance are two main directions in the development of modern microprocessor architectures. In general they are two excluding branches of System-o...
Krzysztof Marcinek, Arkadiusz W. Luczyk, Witold A....
ICCD
1997
IEEE
90views Hardware» more  ICCD 1997»
14 years 1 months ago
TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model
Asynchronous design has a potential of solving many difficulties, such as clock skew and power consumption, which synchronous counterpart suffers with current and future VLSI tech...
Akihiro Takamura, Masashi Kuwako, Masashi Imai, Ta...
MICRO
1995
IEEE
108views Hardware» more  MICRO 1995»
14 years 1 months ago
SPAID: software prefetching in pointer- and call-intensive environments
Software prefetching, typically in the context of numericor loop-intensive benchmarks, has been proposed as one remedy for the performance bottleneck imposed on computer systems b...
Mikko H. Lipasti, William J. Schmidt, Steven R. Ku...
TCAD
2002
158views more  TCAD 2002»
13 years 10 months ago
Static power modeling of 32-bit microprocessors
The paper presents a novel strategy aimed at modelling instruction energy consumption of 32-bits microprocessors. Differently from former approaches, the proposed instruction-level...
Carlo Brandolese, Fabio Salice, William Fornaciari...