DDECS 2009 - PDF Preprint Papers

DDECS 2009 Design and Diagnostics of Electronic Circuits and Systems

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DDECS
2009
IEEE

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Asynchronous two-level logic of reduced cost

14 years 7 months ago

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— We propose a novel synthesis method of a dual-rail asynchronous two-level logic of reduced cost. It is based on a model that operates under so called modified weak constraints....

Igor Lemberski, Petr Fiser

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