Sciweavers

3431 search results - page 25 / 687
» A new instructional operating system
Sort
View
LCPC
1999
Springer
14 years 2 days ago
Instruction Scheduling in the Presence of Java's Runtime Exceptions
One of the challenges present to a Java compiler is Java’s frequent use of runtime exceptions. These exceptions affect performance directly by requiring explicit checks, as wel...
Matthew Arnold, Michael S. Hsiao, Ulrich Kremer, B...
RTSS
1994
IEEE
13 years 12 months ago
Bounding Worst-Case Instruction Cache Performance
The use of caches poses a difficult tradeoff for architects of real-time systems. While caches provide significant performance advantages, they have also been viewed as inherently...
Robert D. Arnold, Frank Mueller, David B. Whalley,...
ICRA
2010
IEEE
134views Robotics» more  ICRA 2010»
13 years 6 months ago
Understanding and executing instructions for everyday manipulation tasks from the World Wide Web
Service robots will have to accomplish more and more complex, open-ended tasks and regularly acquire new skills. In this work, we propose a new approach to generating plans for su...
Moritz Tenorth, Daniel Nyga, Michael Beetz
ICCD
2004
IEEE
87views Hardware» more  ICCD 2004»
14 years 4 months ago
Fetch Halting on Critical Load Misses
As the performance gap between processors and memory systems increases, the CPU spends more time stalled waiting for data from main memory. Critical long latency instructions, suc...
Nikil Mehta, Brian Singer, R. Iris Bahar, Michael ...
ICESS
2007
Springer
14 years 2 months ago
Memory Offset Assignment for DSPs
Compact code generation is very important for an embedded system that has to be implemented on a chip with a severely limited amount of size. Even though on-chip data memory optimi...
Jinpyo Hong, J. Ramanujam