179 search results - page 12 / 36 » A new test pattern generation method for delay fault testing |
DSD
2005
IEEE
14 years 2 months ago
2005
IEEE
Current paper presents new alternatives for accelerating the task of fault simulation for sequential circuits by hardware emulation on FPGA. Fault simulation is an important subta...
ET
2000
13 years 8 months ago
2000
: We present a method for obtaining a minimal set of test configurations and their associated set oftest patterns that completely tests re-programmable Programmable Logic Arrays (P...
VTS
2000
IEEE
14 years 1 months ago
2000
IEEE
We propose a novel BIST technique for non-scan sequential circuits which does not modify the circuit under test. It uses a learning algorithm to build a hardware test sequence gen...
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
To reduce test data volumes, encoded tests and compacted test responses are widely used in industry. Use of test response compaction negatively impacts fault diagnosis since the e...
ATS
1998
IEEE
14 years 1 months ago
1998
IEEE
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...