179 search results - page 27 / 36 » A new test pattern generation method for delay fault testing |
DAC
2002
ACM
14 years 8 months ago
2002
ACM
Software-based self-test (SBST) is emerging as a promising technology for enabling at-speed test of high-speed microprocessors using low-cost testers. We explore the fault diagnos...
SAC
2008
ACM
13 years 7 months ago
2008
ACM
Software-based self-test (SBST) is emerging as a promising technology for enabling at-speed testing of high-speed embedded processors testing in an SoC system. For SBST, test rout...
ATS
2000
IEEE
13 years 12 months ago
2000
IEEE
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...
ATS
2000
IEEE
13 years 12 months ago
2000
IEEE
Testing of embedded cores is very difficult in SOC (system-on-a-chip), since the core user may not know the gate level implementation of the core, and the controllability and obse...
EURODAC
1995
IEEE
13 years 11 months ago
1995
IEEE
: We present a new, dynamic algorithm for test sequence compaction and test cycle reduction for combinationaland sequential circuits. Several dynamic algorithms for compaction in c...