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» A note on fault diagnosis algorithms
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TCAD
2010
105views more  TCAD 2010»
13 years 2 months ago
Fault Tolerant Network on Chip Switching With Graceful Performance Degradation
The structural redundancy inherent to on-chip interconnection networks [networks on chip (NoC)] can be exploited by adaptive routing algorithms in order to provide connectivity eve...
Adán Kohler, Gert Schley, Martin Radetzki
AAAI
2008
13 years 9 months ago
Computing Minimal Diagnoses by Greedy Stochastic Search
Most algorithms for computing diagnoses within a modelbased diagnosis framework are deterministic. Such algorithms guarantee soundness and completeness, but are P 2 hard. To overc...
Alexander Feldman, Gregory M. Provan, Arjan J. C. ...
ET
2006
72views more  ET 2006»
13 years 7 months ago
Optimization of Test/Diagnosis/Rework Location(s) and Characteristics in Electronic System Assembly
In this paper, an optimization methodology is used to select the locations and characteristics of test, diagnosis and rework operations in electronic systems assembly processes. Re...
Zhen Shi, Peter Sandborn
EURODAC
1995
IEEE
137views VHDL» more  EURODAC 1995»
13 years 11 months ago
A formal non-heuristic ATPG approach
This paper presents a formal approach to test combinational circuits. For the sake of explanation we describe the basic algorithms with the help of the stuck–at fault model. Ple...
Manfred Henftling, Hannes C. Wittmann, Kurt Antrei...
DAC
2007
ACM
14 years 8 months ago
Scan Test Planning for Power Reduction
Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can...
Christian G. Zoellin, Hans-Joachim Wunderlich, Jen...