A formal non-heuristic ATPG approach

This paper presents a formal approach to test combinational circuits. For the sake of explanation we describe the basic algorithms with the help of the stuck–at fault model. Please note that due to the flexibility of our approach, various fault models can be handled. A highly efficient data structure, represented by an implication graph, provides a straightforward evaluation of all relevant local and global implications. The experimental results illustrate impressively the effectiveness of our approach. All the MCNC benchmark circuits are processed withoutany aborted fault requiring less CPU–time than state–of–the–art tools.

• Type: Conference
• Year: 1995
• Where: EURODAC
• Authors: Manfred Henftling, Hannes C. Wittmann, Kurt Antreich
• Keywords: EURODAC 1995, Fault Models, Stuck–at Fault Model, Test Combinational Circuits, VHDL