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MICRO
2010
IEEE
99views Hardware» more  MICRO 2010»
13 years 6 months ago
ScalableBulk: Scalable Cache Coherence for Atomic Blocks in a Lazy Environment
Recently-proposed architectures that continuously operate on atomic blocks of instructions (also called chunks) can boost the programmability and performance of shared-memory mult...
Xuehai Qian, Wonsun Ahn, Josep Torrellas
DSN
2009
IEEE
14 years 3 months ago
Decoupling Dynamic Information Flow Tracking with a dedicated coprocessor
Dynamic Information Flow Tracking (DIFT) is a promising security technique. With hardware support, DIFT prevents a wide range of attacks on vulnerable software with minimal perfor...
Hari Kannan, Michael Dalton, Christos Kozyrakis
EMSOFT
2007
Springer
14 years 2 months ago
WCET estimation for executables in the presence of data caches
This paper describes techniques to estimate the worst case execution time of executable code on architectures with data caches. The underlying mechanism is Abstract Interpretation...
Rathijit Sen, Y. N. Srikant
SIGMETRICS
1997
ACM
103views Hardware» more  SIGMETRICS 1997»
14 years 29 days ago
Performance Issues of Enterprise Level Web Proxies
Enterprise level web proxies relay world-wide web traffic between private networks and the Internet. They improve security, save network bandwidth, and reduce network latency. Wh...
Carlos Maltzahn, Kathy J. Richardson, Dirk Grunwal...
DAC
2006
ACM
14 years 9 months ago
Novel full-chip gridless routing considering double-via insertion
As the technology node advances into the nanometer era, via-open defects are one of the dominant failures. To improve via yield and reliability, redundant-via insertion is a highl...
Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lum...