Sciweavers

405 search results - page 34 / 81
» A novel cache architecture with enhanced performance and sec...
Sort
View
IEEEPACT
2006
IEEE
14 years 2 months ago
Two-level mapping based cache index selection for packet forwarding engines
Packet forwarding is a memory-intensive application requiring multiple accesses through a trie structure. The efficiency of a cache for this application critically depends on the ...
Kaushik Rajan, Ramaswamy Govindarajan
ISLPED
2009
ACM
132views Hardware» more  ISLPED 2009»
14 years 3 months ago
Enabling ultra low voltage system operation by tolerating on-chip cache failures
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
LCTRTS
2009
Springer
14 years 3 months ago
Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE)
Instruction fetch behavior has been shown to be very regular and predictable, even for diverse application areas. In this work, we propose the Lookahead Instruction Fetch Engine (...
Stephen Roderick Hines, Yuval Peress, Peter Gavin,...
ICSE
1993
IEEE-ACM
14 years 26 days ago
Formal Approaches to Software Architecture
Over the past 15 years there has been increasing recognition that careful attention to the design of a system’s software architecture is critical to satisfying its requirements ...
David Garlan
ISCA
2009
IEEE
148views Hardware» more  ISCA 2009»
14 years 3 months ago
Memory mapped ECC: low-cost error protection for last level caches
This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of providing error correction for SRAM caches. It is important to limit such overheads as processo...
Doe Hyun Yoon, Mattan Erez