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» A novel high throughput reconfigurable FPGA architecture
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JCP
2008
119views more  JCP 2008»
13 years 8 months ago
Performance Comparisons, Design, and Implementation of RC5 Symmetric Encryption Core using Reconfigurable Hardware
With the wireless communications coming to homes and offices, the need to have secure data transmission is of utmost importance. Today, it is important that information is sent con...
Omar S. Elkeelany, Adegoke Olabisi
ASPDAC
2005
ACM
142views Hardware» more  ASPDAC 2005»
13 years 10 months ago
An AMBA AHB-based reconfigurable SOC architecture using multiplicity of dedicated flyby DMA blocks
– We propose a System-on-Chip (SoC) architecture for reconfigurable applications based on the AMBA HighSpeed Bus (AHB). The architecture features multiple low-area flyby DMA bloc...
Adeoye Olugbon, Sami Khawam, Tughrul Arslan, Ioann...
BMCBI
2010
116views more  BMCBI 2010»
13 years 9 months ago
SEQADAPT: an adaptable system for the tracking, storage and analysis of high throughput sequencing experiments
Background: High throughput sequencing has become an increasingly important tool for biological research. However, the existing software systems for managing and processing these ...
David B. Burdick, Christopher C. Cavnor, Jeremy Ha...
NOCS
2010
IEEE
13 years 6 months ago
Design of a High-Throughput Distributed Shared-Buffer NoC Router
Router microarchitecture plays a central role in the performance of an on-chip network (NoC). Buffers are needed in routers to house incoming flits which cannot be immediately forw...
Rohit Sunkam Ramanujam, Vassos Soteriou, Bill Lin,...
FPL
2008
Springer
153views Hardware» more  FPL 2008»
13 years 10 months ago
Exploring FPGA network on chip implementations across various application and network loads
Abstract-The network on chip will become a future general purpose interconnect for FPGAs much like today's standard OPB or PLB bus architectures. However, performance characte...
Graham Schelle, Dirk Grunwald