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DAC
2010
ACM
13 years 9 months ago
RAMP gold: an FPGA-based architecture simulator for multiprocessors
We present RAMP Gold, an economical FPGA-based architecture simulator that allows rapid early design-space exploration of manycore systems. The RAMP Gold prototype is a high-throu...
Zhangxi Tan, Andrew Waterman, Rimas Avizienis, Yun...
EUROPAR
2010
Springer
13 years 10 months ago
Efficient Address Mapping of Shared Cache for On-Chip Many-Core Architecture
Abstract. Performance of the on-chip cache is critical for processor. The multithread program model usually employed by on-chip many-core architectures may have effects on cache ac...
Fenglong Song, Dongrui Fan, Zhiyong Liu, Junchao Z...
EPS
1995
Springer
14 years 20 days ago
PANIC: A Parallel Evolutionary Rule Based System
PANIC (Parallelism And Neural networks In Classifier systems) is a parallel system to evolve behavioral strategies codified by sets of rules. It integrates several adaptive techni...
Antonella Giani, Fabrizio Baiardi, Antonina Starit...
DEBS
2008
ACM
13 years 11 months ago
A framework for performance evaluation of complex event processing systems
Several new Complex Event Processing (CEP) engines have been recently released, many of which are intended to be used in performance sensitive scenarios - like fraud detection, tr...
Marcelo R. N. Mendes, Pedro Bizarro, Paulo Marques
HPCA
1997
IEEE
14 years 1 months ago
Global Address Space, Non-Uniform Bandwidth: A Memory System Performance Characterization of Parallel Systems
Many parallel systems offer a simple view of memory: all storage cells are addresseduniformly. Despite a uniform view of the memory, the machines differsignificantly in theirmemo...
Thomas Stricker, Thomas R. Gross