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» A power-configurable bus for embedded systems
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SIES
2008
IEEE
14 years 1 months ago
Performance evaluation of a java chip-multiprocessor
—Chip multiprocessing design is an emerging trend for embedded systems. In this paper, we introduce a Java multiprocessor system-on-chip called JopCMP. It is a symmetric shared-m...
Christof Pitter, Martin Schoeberl
WSNA
2003
ACM
14 years 18 days ago
Analyzing and modeling encryption overhead for sensor network nodes
Recent research in sensor networks has raised security issues for small embedded devices. Security concerns are motivated by the deployment of a large number of sensory devices in...
Prasanth Ganesan, Ramnath Venugopalan, Pushkin Ped...
DAC
2009
ACM
14 years 8 months ago
Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis
In this paper, a design method for automotive architectures is proposed. The two main technical contributions are (i) a novel hardware/software architecture encoding that unifies ...
Jürgen Teich, Martin Lukasiewycz, Michael Gla...
RTAS
2007
IEEE
14 years 1 months ago
Full Duplex Switched Ethernet for Next Generation "1553B"-Based Applications
Over the last thirty years, the MIL-STD 1553B data bus has been used in many embedded systems, like aircrafts, ships, missiles and satellites. However, the increasing number and c...
Ahlem Mifdaoui, Fabrice Frances, Christian Fraboul
IPPS
2007
IEEE
14 years 1 months ago
Splice: A Standardized Peripheral Logic and Interface Creation Engine
Recent advancements in FPGA technology have allowed manufacturers to place general-purpose processors alongside user-configurable logic gates on a single chip. At first glance, ...
Justin Thiel, Ron K. Cytron