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ICPP
2009
IEEE
14 years 2 months ago
Bank-aware Dynamic Cache Partitioning for Multicore Architectures
Abstract—As Chip-Multiprocessor systems (CMP) have become the predominant topology for leading microprocessors, critical components of the system are now integrated on a single c...
Dimitris Kaseridis, Jeffrey Stuecheli, Lizy K. Joh...
RTCSA
1998
IEEE
13 years 12 months ago
Partition Scheduling in APEX Runtime Environment for Embedded Avionics Software
Advances in the computer technology encouraged the avionics industry to replace the federated design of control units with an integrated suite of control modules that share the co...
Yann-Hang Lee, Daeyoung Kim, Mohamed F. Younis, Je...
JSAC
2006
147views more  JSAC 2006»
13 years 7 months ago
Smart pay access control via incentive alignment
We use game theorectic models to show the lack of incentives in the TCP congestion avoidance algorithm and the consequential systemwide network problems. We then propose a Vickery-...
Jun Shu, Pravin Varaiya
IEEEPACT
2006
IEEE
14 years 1 months ago
A low-cost memory remapping scheme for address bus protection
The address sequence on the processor-memory bus can reveal abundant information about the control flow of a program. This can lead to critical information leakage such as encryp...
Lan Gao, Jun Yang 0002, Marek Chrobak, Youtao Zhan...
ET
2007
101views more  ET 2007»
13 years 7 months ago
Towards Nanoelectronics Processor Architectures
In this paper, we focus on reliability, one of the most fundamental and important challenges, in the nanoelectronics environment. For a processor architecture based on the unreliab...
Wenjing Rao, Alex Orailoglu, Ramesh Karri