Bank-aware Dynamic Cache Partitioning for Multicore Architectures

Abstract—As Chip-Multiprocessor systems (CMP) have become the predominant topology for leading microprocessors, critical components of the system are now integrated on a single chip. This enables sharing of computation resources that was not previously possible. In addition, the virtualization of these computational resources exposes the system to a mix of diverse and competing workloads. Cache is a resource of primary concern as it can be dominant in controlling overall throughput. In order to prevent destructive interference between divergent workloads, the last level of cache must be partitioned. In the past, many solutions have been proposed but most of them are assuming either simplified cache hierarchies with no realistic restrictions or complex cache schemes that are difficult to integrate in a real design. To address this problem, we propose a dynamic partitioning strategy based on realistic last level cache designs of CMP processors. We used a cycle accurate, full system s...

• Type: Conference
• Year: 2009
• Where: ICPP
• Authors: Dimitris Kaseridis, Jeffrey Stuecheli, Lizy K. John
• Keywords: Cache, Complex Cache Schemes, Distributed And Parallel Computing, ICPP 2009, Level Cache Designs