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ICCAD
1997
IEEE
90views Hardware» more  ICCAD 1997»
14 years 2 months ago
A hierarchical decomposition methodology for multistage clock circuits
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar
ICPP
2002
IEEE
14 years 3 months ago
Optimal Code Size Reduction for Software-Pipelined Loops on DSP Applications
Code size expansion of software-pipelined loops is a critical problem for DSP systems with strict code size constraint. Some ad-hoc code size reduction techniques were used to try...
Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha
ESA
2006
Springer
140views Algorithms» more  ESA 2006»
14 years 1 months ago
Latency Constrained Aggregation in Sensor Networks
A sensor network consists of sensing devices which may exchange data through wireless communication. A particular feature of sensor networks is that they are highly energy constrai...
Luca Becchetti, Peter Korteweg, Alberto Marchetti-...
IPPS
2007
IEEE
14 years 4 months ago
Power-Aware Speedup
Power-aware processors operate in various power modes to reduce energy consumption with a corresponding decrease in peak processor throughput. Recent work has shown power-aware cl...
Rong Ge, Kirk W. Cameron
IFIP
2007
Springer
14 years 4 months ago
Elliptic Control by Penalty Techniques with Control Reduction
The paper deals with the numerical treatment of optimal control problems with bounded distributed controls and elliptic state equations by a wider class of barrier-penalty methods...
Christian Grossmann, Holger Kunz, Robert Meischner