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HPCA
2006
IEEE
14 years 8 months ago
The common case transactional behavior of multithreaded programs
Transactional memory (TM) provides an easy-to-use and high-performance parallel programming model for the upcoming chip-multiprocessor systems. Several researchers have proposed a...
JaeWoong Chung, Hassan Chafi, Chi Cao Minh, Austen...
ISPASS
2009
IEEE
14 years 2 months ago
WARP: Enabling fast CPU scheduler development and evaluation
Abstract—Developing CPU scheduling algorithms and understanding their impact in practice can be difficult and time consuming due to the need to modify and test operating system ...
Haoqiang Zheng, Jason Nieh
JVM
2004
165views Education» more  JVM 2004»
13 years 9 months ago
Using Hardware Performance Monitors to Understand the Behavior of Java Applications
Modern Java programs, such as middleware and application servers, include many complex software components. Improving the performance of these Java applications requires a better ...
Peter F. Sweeney, Matthias Hauswirth, Brendon Caho...
SIGMETRICS
2005
ACM
110views Hardware» more  SIGMETRICS 2005»
14 years 1 months ago
Empirical evaluation of multi-level buffer cache collaboration for storage systems
To bridge the increasing processor-disk performance gap, buffer caches are used in both storage clients (e.g. database systems) and storage servers to reduce the number of slow di...
Zhifeng Chen, Yan Zhang, Yuanyuan Zhou, Heidi Scot...
ISCI
2007
152views more  ISCI 2007»
13 years 7 months ago
Evaluating digital video recorder systems using analytic hierarchy and analytic network processes
Digital video recorder (DVR) systems are novel security products with significant potential for application in the surveillance market, which, like many other areas of security t...
Che-Wei Chang, Cheng-Ru Wu, Chin-Tsai Lin, Hung-Lu...