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» A reuse scenario for the VHDL-based hardware design flow
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CODES
2009
IEEE
13 years 11 months ago
Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems
Field-Programmable Gate Arrays (FPGAs) have become promising mapping fabric for the implementation of System-on-Chip (SoC) platforms, due to their large capacity and their enhance...
Vincenzo Rana, Srinivasan Murali, David Atienza, M...
ASPDAC
2007
ACM
120views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Integrating Power Management into Distributed Real-time Systems at Very Low Implementation Cost
The development cost of low-power embedded systems can be significantly reduced by reusing legacy designs and applying proper modifications to meet the new power constraints. The ...
Bita Gorjiara, Nader Bagherzadeh, Pai H. Chou
ICECCS
2005
IEEE
125views Hardware» more  ICECCS 2005»
14 years 29 days ago
Model Checking Live Sequence Charts
Live Sequence Charts (LSCs) are a broad extension to Message Sequence Charts (MSCs) to capture complex interobject communication rigorously. A tool support for LSCs, named PlayEng...
Jun Sun 0001, Jin Song Dong
CASES
2008
ACM
13 years 9 months ago
Active control and digital rights management of integrated circuit IP cores
We introduce the first approach that can actively control multiple hardware intellectual property (IP) cores used in an integrated circuit (IC). The IP rights owner(s) can remotel...
Yousra Alkabani, Farinaz Koushanfar
WWW
2005
ACM
14 years 8 months ago
A service creation environment based on end to end composition of Web services
The demand for quickly delivering new applications is increasingly becoming a business imperative today. Application development is often done in an ad hoc manner, without standar...
Vikas Agarwal, Koustuv Dasgupta, Neeran M. Karnik,...