1017 search results - page 130 / 204 » A routing algorithm for flip-chip design |
ISPD
2003
ACM
14 years 29 days ago
2003
ACM
Floorplanning individual pipelined array modules of a larger overall die can yield beneficial results. Critical paths in every pipeline stage of a pipelined design are roughly equ...
SAMOS
2004
Springer
14 years 1 months ago
2004
Springer
Abstract. In this work we present CoDeL (Controller Description Language), a framework for rapidly prototyping policy specific controllers for routers in interconnection networks....
INFOCOM
2000
IEEE
14 years 3 days ago
2000
IEEE
—We propose a framework for the creation and maintenance of multicast trees in hierarchical ATM networks. This framework aims at coping with an inherent difficulty of topology a...
IPPS
1998
IEEE
13 years 12 months ago
1998
IEEE
We describe a family of reconfigurable parallel architectures for logic emulation. They are supposed to be applicable like conventional FPGAs, while covering a larger range of circ...
FPL
2009
Springer
13 years 11 months ago
2009
Springer
This paper investigates the challenges of run-time resource management in future coarse-grained network-onreconfigurable-chips (NoRCs). Run-time reconfiguration is a key feature e...