30 search results - page 4 / 6 » A routing approach to reduce glitches in low power FPGAs |
ISVLSI
2007
IEEE
14 years 1 months ago
2007
IEEE
As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the m...
ANCS
2008
ACM
13 years 9 months ago
2008
ACM
Today's routers need to perform packet classification at wire speed in order to provide critical services such as traffic billing, priority routing and blocking unwanted Inte...
SLIP
2009
ACM
14 years 1 months ago
2009
ACM
A novel high-level approach for estimating power consumption of global interconnects in data-path oriented designs implemented in FPGAs is presented. The methodology is applied to...
FCCM
2003
IEEE
14 years 12 days ago
2003
IEEE
Although domain-specialized FPGAs can offer significant area, speed and power improvements over conventional reconfigurable devices, there are several unique and unexplored design...
MONET
2006
13 years 7 months ago
2006
Several applications have been envisioned for multihop wireless networks that require different qualities of service from the network. In order to support such applications, the n...