11 search results - page 2 / 3 » A runtime system for software lock elision |
ISCA
2007
IEEE
14 years 2 months ago
2007
IEEE
Speculative compiler optimizations are effective in improving both single-thread performance and reducing power consumption, but their implementation introduces significant compl...
CGO
2006
IEEE
14 years 2 months ago
2006
IEEE
Software code caches are increasingly being used to amortize the runtime overhead of dynamic optimizers, simulators, emulators, dynamic translators, dynamic compilers, and other t...
ECRTS
2006
IEEE
14 years 2 months ago
2006
IEEE
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
MICRO
2010
IEEE
13 years 7 months ago
2010
IEEE
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
IEEEPACT
2007
IEEE
14 years 2 months ago
2007
IEEE
Transactional Memory (TM) simplifies parallel programming by supporting atomic and isolated execution of user-identified tasks. To date, TM programming has required the use of l...