129 search results - page 6 / 26 » A scalable architecture for maintaining packet latency measu... |
ICPP
1993
IEEE
13 years 11 months ago
1993
IEEE
Scalability of parallel architectures is an interesting area of current research. Shared memory parallel programming is attractive stemming from its relative ease in transitioning...
ISCAPDCS
2004
13 years 9 months ago
2004
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...
INFOCOM
1999
IEEE
13 years 11 months ago
1999
IEEE
We consider designing near video on demand (VoD) systems that minimize start-up latency while maintaining high image quality. Recently several research teams have developed period...
AHS
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper describes the architecture of our dynamically reconfigurable Network-on-Chip (NoC) architecture that has been proposed for reconfigurable Multiprocessor system-on-chip ...
ICCD
2008
IEEE
14 years 4 months ago
2008
IEEE
- In this paper, we analyze the impact of network contention on the application mapping for tile-based Networkon-Chip (NoC) architectures. Our main theoretical contribution consist...