Sciweavers

359 search results - page 10 / 72
» A section cache system designed for VLIW architectures
Sort
View
SBACPAD
2003
IEEE
135views Hardware» more  SBACPAD 2003»
14 years 26 days ago
Adaptive Compressed Caching: Design and Implementation
In this paper, we reevaluate the use of adaptive compressed caching to improve system performance through the reduction of accesses to the backing stores. We propose a new adaptab...
Rodrigo S. de Castro, Alair Pereira do Lago, Dilma...
DAC
2003
ACM
14 years 26 days ago
Improved indexing for cache miss reduction in embedded systems
The increasing use of microprocessor cores in embedded systems as well as mobile and portable devices creates an opportunity for customizing the cache subsystem for improved perfo...
Tony Givargis
ICS
2010
Tsinghua U.
13 years 10 months ago
The auction: optimizing banks usage in Non-Uniform Cache Architectures
The growing influence of wire delay in cache design has meant that access latencies to last-level cache banks are no longer constant. Non-Uniform Cache Architectures (NUCAs) have ...
Javier Lira, Carlos Molina, Antonio Gonzále...
ICPP
2006
IEEE
14 years 1 months ago
Data Transfers between Processes in an SMP System: Performance Study and Application to MPI
— This paper focuses on the transfer of large data in SMP systems. Achieving good performance for intranode communication is critical for developing an efficient communication s...
Darius Buntinas, Guillaume Mercier, William Gropp
ISCA
1996
IEEE
103views Hardware» more  ISCA 1996»
13 years 11 months ago
Evaluation of Design Alternatives for a Multiprocessor Microprocessor
In the future, advanced integrated circuit processing and packaging technology will allow for several design options for multiprocessor microprocessors. In this paper we consider ...
Basem A. Nayfeh, Lance Hammond, Kunle Olukotun