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» A section cache system designed for VLIW architectures
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CCS
2008
ACM
13 years 9 months ago
Deconstructing new cache designs for thwarting software cache-based side channel attacks
Software cache-based side channel attacks present a serious threat to computer systems. Previously proposed countermeasures were either too costly for practical use or only effect...
Jingfei Kong, Onur Aciiçmez, Jean-Pierre Se...
ISCAS
2007
IEEE
104views Hardware» more  ISCAS 2007»
14 years 1 months ago
Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors
Process variation in future technologies can cause severe performance degradation since different parts of the shared Register File (RF) in VLIW processors may operate at various ...
Praveen Raghavan, José L. Ayala, David Atie...
FPL
2009
Springer
135views Hardware» more  FPL 2009»
14 years 7 days ago
Fast critical sections via thread scheduling for FPGA-based multithreaded processors
As FPGA-based systems including soft processors become increasingly common, we are motivated to better understand the architectural trade-offs and improve the efficiency of these...
Martin Labrecque, J. Gregory Steffan
ICCD
1999
IEEE
122views Hardware» more  ICCD 1999»
13 years 12 months ago
Design and Evaluation of a Selective Compressed Memory System
This research explores any potential for an on-chip cache compression which can reduce not only cache miss ratio but also miss penalty, if main memory is also managed in compresse...
Jang-Soo Lee, Won-Kee Hong, Shin-Dug Kim
ISORC
2011
IEEE
12 years 11 months ago
A Time-Predictable Object Cache
—Static cache analysis for data allocated on the heap is practically impossible for standard data caches. We propose a distinct object cache for heap allocated data. The cache is...
Martin Schoeberl