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ICCAD
1995
IEEE
129views Hardware» more  ICCAD 1995»
13 years 11 months ago
Activity-driven clock design for low power circuits
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
Gustavo E. Téllez, Amir H. Farrahi, Majid S...
SIPS
2006
IEEE
14 years 1 months ago
Architecture-Aware LDPC Code Design for Software Defined Radio
Low-Density Parity-Check (LDPC) codes have been adopted in the physical layer of many communication systems because of their superior performance. The direct implementation of the...
Yuming Zhu, Chaitali Chakrabarti
TVLSI
2008
133views more  TVLSI 2008»
13 years 7 months ago
A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fi...
Mitchell J. Myjak, José G. Delgado-Frias
ICC
2009
IEEE
106views Communications» more  ICC 2009»
14 years 2 months ago
Pilot Matrix Design for Interim Channel Estimation in Two-Hop MIMO AF Relay Systems
In this paper, we are concerned with a two-hop multi-input-multi-output (MIMO) amplify-andforward (AF) relay system consisting of a source node (SN), a relay node (RN), and a dest...
Jun Ma, Philip V. Orlik, Jinyun Zhang, Ye (Geoffre...
ICCAD
2009
IEEE
136views Hardware» more  ICCAD 2009»
13 years 5 months ago
Multi-functional interconnect co-optimization for fast and reliable 3D stacked ICs
Heat removal and power delivery have become two major reliability concerns in 3D stacked IC technology. For thermal problem, two possible solutions exist: thermal-through-silicon-...
Young-Joon Lee, Rohan Goel, Sung Kyu Lim