ICCAD 2009 - PDF Preprint Papers

ICCAD 2009 International Conference on Computer-Aided Design

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ICCAD
2009
IEEE

198views Hardware» more ICCAD 2009»

Battery allocation for wireless sensor network lifetime maximization under cost constraints

13 years 10 months ago

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Wireless sensor networks hold the potential to open new domains to distributed data acquisition. However, such networks are prone to premature failure because some nodes deplete t...

Hengyu Long, Yongpan Liu, Yiqun Wang, Robert P. Di...

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Id	Views	Title	Status

1	198	Battery allocation for wireless sensor network lifetime maximization under cost constraints	claim
2	179	Automatic memory partitioning and scheduling for throughput and power optimization	claim
3	171	A hybrid local-global approach for multi-core thermal management	claim
4	161	The epsilon-approximation to discrete VT assignment for leakage power minimization	claim
5	159	First steps towards SAT-based formal analog verification	claim
6	154	Pad assignment for die-stacking System-in-Package design	claim
7	152	Adaptive sampling for efficient failure probability analysis of SRAM cells	claim
8	151	GREMA: Graph reduction based efficient mask assignment for double patterning technology	claim
9	151	Timing yield-aware color reassignment and detailed placement perturbation for double patterning lithography	claim
10	147	SAT-based protein design	claim
11	144	Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits	claim
12	136	A hierarchical floating random walk algorithm for fabric-aware 3D capacitance extraction	claim
13	136	Multi-functional interconnect co-optimization for fast and reliable 3D stacked ICs	claim
14	135	Enhanced reliability-aware power management through shared recovery technique	claim
15	133	A parallel preconditioning strategy for efficient transistor-level circuit simulation	claim
16	132	DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior	claim
17	131	Scheduling with soft constraints	claim
18	129	A study of Through-Silicon-Via impact on the 3D stacked IC layout	claim
19	128	PCRAMsim: System-level performance, energy, and area modeling for Phase-Change RAM	claim
20	126	Timing Arc based logic analysis for false noise reduction	claim
21	125	CROP: Fast and effective congestion refinement of placement	claim
22	123	Multi-level clustering for clock skew optimization	claim
23	121	MOLES: Malicious off-chip leakage enabled by side-channels	claim
24	119	Iterative layering: Optimizing arithmetic circuits by structuring the information flow	claim
25	118	Characterizing within-die variation from multiple supply port IDDQ measurements	claim
26	118	Pre-bond testable low-power clock tree design for 3D stacked ICs	claim
27	118	Memory organization and data layout for instruction set extensions with architecturally visible storage	claim
28	117	Binning optimization based on SSTA for transparently-latched circuits	claim
29	113	A performance analytical model for Network-on-Chip with constant service time routers	claim
30	109	Energy reduction for STT-RAM using early write termination	claim
31	109	CRISP: Congestion reduction by iterated spreading during placement	claim
32	106	An efficient pre-assignment routing algorithm for flip-chip designs	claim
33	106	Quantifying robustness metrics in parameterized static timing analysis	claim
34	102	Power-switch routing for coarse-grain MTCMOS technologies	claim
35	101	Compacting test vector sets via strategic use of implications	claim
36	100	A study of routability estimation and clustering in placement	claim
37	98	GHM: A generalized Hamiltonian method for passivity test of impedance/admittance descriptor systems	claim
38	98	A rigorous framework for convergent net weighting schemes in timing-driven placement	claim
39	96	PSTA-based branch and bound approach to the silicon speedpath isolation problem	claim
40	94	Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint	claim
41	93	An efficient wakeup scheduling considering resource constraint for sensor-based power gating designs	claim
42	92	How to consider shorts and guarantee yield rate improvement for redundant wire insertion	claim
43	89	Decoupling capacitance efficient placement for reducing transient power supply noise	claim
44	88	IPR: In-Place Reconfiguration for FPGA fault tolerance	claim
45	87	The synthesis of combinational logic to generate probabilities	claim
46	87	Mitigation of intra-array SRAM variability using adaptive voltage architecture	claim
47	85	Synthesizing complementary circuits automatically	claim
48	82	Operating system scheduling for efficient online self-test in robust systems	claim
49	66	Joint design-time and post-silicon optimization for digitally tuned analog circuits	claim

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