61 search results - page 6 / 13 » A simultaneous routing tree construction and fanout optimiza... |
ISPD
2006
ACM
14 years 1 months ago
2006
ACM
Advances in VLSI technology make clock skew more susceptible to process variations. Notwithstanding efficient zero skew routing algorithms, clock skew still limits post-manufactu...
ISVLSI
2007
IEEE
14 years 1 months ago
2007
IEEE
As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the m...
TCAD
2008
13 years 7 months ago
2008
Abstract--Advances in very large-scale integration technology make clock skew more susceptible to process variations. Notwithstanding efficient exact zero-skew algorithms, clock sk...
DATE
2002
IEEE
14 years 17 days ago
2002
IEEE
In this paper, we address the problem of simultaneous routing and buffer insertion. Recently in [12, 22], the authors considered simultaneous maze routing and buffer insertion und...
CN
2007
13 years 7 months ago
2007
— Multipath routing (MPR) is an effective strategy to achieve robustness, load balancing, congestion reduction, and increased throughput in computer networks. Disjoint multipath ...