Sciweavers

132 search results - page 18 / 27
» A statistical multiprocessor cache model
Sort
View
WDAG
2005
Springer
82views Algorithms» more  WDAG 2005»
14 years 3 months ago
Distributed Transactional Memory for Metric-Space Networks
Transactional Memory is a concurrent programming API in which concurrent threads synchronize via transactions (instead of locks). Although this model has mostly been studied in the...
Maurice Herlihy, Ye Sun
HICSS
1999
IEEE
121views Biometrics» more  HICSS 1999»
14 years 2 months ago
Evaluation of the JIAJIA Software DSM System on High Performance Computer Architectures
Distributed Shared Memory (DSM) combines the scalability of loosely coupled multicomputer systems with the ease of usability of tightly coupled multiprocessors, and allows transpa...
M. Rasit Eskicioglu, T. Anthony Marsland, Weiwu Hu...
DATE
2010
IEEE
178views Hardware» more  DATE 2010»
14 years 2 months ago
Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability
—With every process generation, the problem of variability in physical parameters and environmental conditions poses a great challenge to the design of fast and reliable circuits...
Shrikanth Ganapathy, Ramon Canal, Antonio Gonz&aac...
EDBT
2010
ACM
151views Database» more  EDBT 2010»
14 years 2 months ago
Warm cache costing: a feedback optimization technique for buffer pool aware costing
Most modern RDBMS depend on the query processing optimizer’s cost model to choose the best execution plan for a given query. Since the physical IO (PIO) is a costly operation to...
H. S. Ramanujam, Edwin Seputis
IPPS
2010
IEEE
13 years 7 months ago
A PRAM-NUMA model of computation for addressing low-TLP workloads
It is possible to implement the parallel random access machine (PRAM) on a chip multiprocessor (CMP) efficiently with an emulated shared memory (ESM) architecture to gain easy par...
Martti Forsell