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» A study of slipstream processors
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148
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CF
2007
ACM
15 years 7 months ago
An analysis of the effects of miss clustering on the cost of a cache miss
In this paper we describe a new technique, called pipeline spectroscopy, and use it to measure the cost of each cache miss. The cost of a miss is displayed (graphed) as a histogra...
Thomas R. Puzak, Allan Hartstein, Philip G. Emma, ...
137
Voted
ISCA
1995
IEEE
110views Hardware» more  ISCA 1995»
15 years 7 months ago
Optimization of Instruction Fetch Mechanisms for High Issue Rates
Recent superscalar processors issue four instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be expl...
Thomas M. Conte, Kishore N. Menezes, Patrick M. Mi...
130
Voted
SPAA
1995
ACM
15 years 7 months ago
Parallel Sorting with Limited Bandwidth
We study the problem of sorting on a parallel computer with limited communication bandwidth. By using the PRAM(m) model, where p processors communicate through a globally shared me...
Micah Adler, John W. Byers, Richard M. Karp
DSD
2009
IEEE
118views Hardware» more  DSD 2009»
15 years 7 months ago
On the Risk of Fault Coupling over the Chip Substrate
—Duplication and comparison has proven to be an efficient method for error detection. Based on this generic principle dual core processor architectures with output comparison ar...
Peter Tummeltshammer, Andreas Steininger
138
Voted
LCTRTS
2010
Springer
15 years 5 months ago
An efficient code update scheme for DSP applications in mobile embedded systems
DSP processors usually provide dedicated address generation units (AGUs) to assist address computation. By carefully allocating variables in the memory, DSP compilers take advanta...
Weijia Li, Youtao Zhang