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» A study of slipstream processors
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JISE
1998
84views more  JISE 1998»
13 years 10 months ago
Determining the Idle Time of a Tiling: New Results
In the framework of perfect loop nests with uniform dependences, tiling has been extensively studied as a source-to-source program transformation. We build upon recent results by ...
Frederic Desprez, Jack Dongarra, Fabrice Rastello,...
ISCA
2010
IEEE
237views Hardware» more  ISCA 2010»
13 years 8 months ago
High performance cache replacement using re-reference interval prediction (RRIP)
Practical cache replacement policies attempt to emulate optimal replacement by predicting the re-reference interval of a cache block. The commonly used LRU replacement policy alwa...
Aamer Jaleel, Kevin B. Theobald, Simon C. Steely J...
JCM
2010
119views more  JCM 2010»
13 years 8 months ago
Evaluation of Router Implementations for Explicit Congestion Control Schemes
— Explicit congestion control schemes use router feedback to overcome limitations of the standard mechanisms of the Transmission Control Protocol (TCP). These approaches require ...
Simon Hauger, Michael Scharf, Jochen Kögel, C...
IPPS
2010
IEEE
13 years 8 months ago
Adapting cache partitioning algorithms to pseudo-LRU replacement policies
Abstract-- Recent studies have shown that cache partitioning is an efficient technique to improve throughput, fairness and Quality of Service (QoS) in CMP processors. The cache par...
Kamil Kedzierski, Miquel Moretó, Francisco ...
WAOA
2010
Springer
246views Algorithms» more  WAOA 2010»
13 years 8 months ago
Tradeoff between Energy and Throughput for Online Deadline Scheduling
The past few years have witnessed a number of interesting online algorithms for deadline scheduling in the dynamic speed scaling model (in which a processor can vary its speed to ...
Ho-Leung Chan, Tak Wah Lam, Rongbin Li