1137 search results - page 123 / 228 » A study of slipstream processors |
IPPS
1998
IEEE
14 years 2 months ago
1998
IEEE
In the study of PetaFlop project, Processor-In-Memory array was proposed to be a target architecture in achieving 1015 floating point operations per second computing performance. ...
ISCA
1998
IEEE
14 years 2 months ago
1998
IEEE
Explicitly Parallel Instruction Computing (EPIC) architectures require the compiler to express program instruction level parallelism directly to the hardware. EPIC techniques whic...
ICDCS
1997
IEEE
14 years 2 months ago
1997
IEEE
Clusters of workstations are increasingly being viewed as a cost-e ective alternative to parallel supercomputers. However, resource management and scheduling on workstations clust...
ISCA
1997
IEEE
14 years 2 months ago
1997
IEEE
Superscalar processors currently have the potential to fetch multiple basic blocks per cycle by employing one of several recently proposed instruction fetch mechanisms. However, t...
ASPLOS
1996
ACM
14 years 2 months ago
1996
ACM
New high-speed networks greatly encourage the use of network memory as a cache for virtual memory and file pages, thereby reducing the need for disk access. Becausepages are the f...