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» A study of slipstream processors
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EUROPAR
2009
Springer
14 years 2 months ago
High Performance Matrix Multiplication on Many Cores
Moore’s Law suggests that the number of processing cores on a single chip increases exponentially. The future performance increases will be mainly extracted from thread-level par...
Nan Yuan, Yongbin Zhou, Guangming Tan, Junchao Zha...
GECCO
2009
Springer
156views Optimization» more  GECCO 2009»
14 years 2 months ago
Characterizing the genetic programming environment for fifth (GPE5) on a high performance computing cluster
Solving complex, real-world problems with genetic programming (GP) can require extensive computing resources. However, the highly parallel nature of GP facilitates using a large n...
Kenneth Holladay
SLE
2009
Springer
14 years 2 months ago
Language Evolution in Practice: The History of GMF
In consequence of changing requirements and technological progress, software languages are subject to change. The changes affect the language’s specification, which in turn a...
Markus Herrmannsdoerfer, Daniel Ratiu, Guido Wachs...
DATE
2008
IEEE
107views Hardware» more  DATE 2008»
14 years 2 months ago
Instruction Set Extension Exploration in Multiple-Issue Architecture
To satisfy high-performance computing demand in modern embedded devices, current embedded processor architectures provide designer with possibility either to define customized ins...
I-Wei Wu, Zhi-Yuan Chen, Jean Jyh-Jiun Shann, Chun...
DSD
2008
IEEE
124views Hardware» more  DSD 2008»
14 years 2 months ago
A Modular Approach to Model Heterogeneous MPSoC at Cycle Level
This paper proposes a system-level cycle-based framework to model and design heterogeneous Multiprocessor Systems on-Chip (MPSoC), called GRAPES. The approach features flexibilit...
Matteo Monchiero, Gianluca Palermo, Cristina Silva...