Hardware transactional memory should support unbounded transactions: transactions of arbitrary size and duration. We describe a hardware implementation of unbounded transactional ...
C. Scott Ananian, Krste Asanovic, Bradley C. Kuszm...
In this paper we present an automated way of using spare CPU resources within a shared memory multi-processor or multi-core machine. Our approach is (i) to profile the execution o...
As transistor process technology approaches the nanometer scale, process variation significantly affects the design and optimization of high performance microprocessors. Prior stu...
—Various studies have pointed out the debilitating effects of OS Jitter on the performance of parallel applications on large clusters such as the ASCI Purple and the Mare Nostrum...
The growing complexity of modern processors has made the generation of highly efficient code increasingly difficult. Manual code generation is very time consuming, but it is oft...