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» A succinct memory model for automated design debugging
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ASPLOS
2006
ACM
13 years 10 months ago
Efficiently exploring architectural design spaces via predictive modeling
Architects use cycle-by-cycle simulation to evaluate design choices and understand tradeoffs and interactions among design parameters. Efficiently exploring exponential-size desig...
Engin Ipek, Sally A. McKee, Rich Caruana, Bronis R...
FTCS
1998
79views more  FTCS 1998»
13 years 8 months ago
Proving Correctness of a Controller Algorithm for the RAID Level 5 System
Most RAID controllers implemented in industry are complicated and di cult to reason about. This complexity has led to software and hardware systems that are di cult to debug and h...
Mandana Vaziri, Nancy A. Lynch, Jeannette M. Wing
DAC
2007
ACM
14 years 7 months ago
A System For Coarse Grained Memory Protection In Tiny Embedded Processors
Many embedded systems contain resource constrained microcontrollers where applications, operating system components and device drivers reside within a single address space with no...
Ram Kumar, Akhilesh Singhania, Andrew Castner, Edd...
TVLSI
2008
124views more  TVLSI 2008»
13 years 6 months ago
A Refinement-Based Compositional Reasoning Framework for Pipelined Machine Verification
Abstract--We present a refinement-based compositional framework for showing that pipelined machines satisfy the same safety and liveness properties as their non-pipelined specifica...
Panagiotis Manolios, Sudarshan K. Srinivasan
EMSOFT
2008
Springer
13 years 8 months ago
Randomized directed testing (REDIRECT) for Simulink/Stateflow models
The Simulink/Stateflow (SL/SF) environment from Mathworks is becoming the de facto standard in industry for model based development of embedded control systems. Many commercial to...
Manoranjan Satpathy, Anand Yeolekar, S. Ramesh