853 search results - page 3 / 171 » A supporting system for verification among models of the UML |
UML
2001
Springer
14 years 3 days ago
2001
Springer
: There are several reasons to specify UML models in a formal way The most important are to avoid inconsistencies and ambiguities and to do verification and forecasting of system p...
UML
2004
Springer
14 years 1 months ago
2004
Springer
Abstract. In this paper, we propose a verification methodology for System-OnChip (SoC) design using Unified Modeling Language (UML). We introduce UML as a formal model to analyze a...
ECMDAFA
2005
Springer
14 years 1 months ago
2005
Springer
This article presents a control flow analysis methodology based on UML 2.0 sequence diagrams (SD). In contrast to the conventional code-based control flow analysis techniques, thi...
VVEIS
2008
13 years 9 months ago
2008
This paper presents an executable semantics of OO models. We made it possible to conduct both simulation and theorem proving on the semantics by implementing its underlying heap me...
AOSD
2009
ACM
14 years 2 months ago
2009
ACM
e is an aspect-oriented hardware verification language that is widely used to verify the design of electronic circuits through the development and execution of testbenches. In rec...