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CISIS
2009
IEEE
14 years 3 months ago
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints
—Regular multi-core processors are appearing in the embedded system market as high performance software programmable solutions. The use of regular interconnect fabrics for them a...
Francisco Gilabert Villamón, Daniele Ludovi...
ISOLA
2010
Springer
13 years 7 months ago
A Theory of Mediators for Eternal Connectors
On the fly synthesis of mediators is a revolutionary approach to the seamless networking of today’s and future digital systems that increasingly need be connected. The resulting...
Paola Inverardi, Valérie Issarny, Romina Sp...
SLIP
2006
ACM
14 years 2 months ago
Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture
— The increasing gap between design productivity and chip complexity and the emerging Systems-On-Chip (SOC) architectural template have led to the wide utilization of reusable ha...
Jin Guo, Antonis Papanikolaou, Pol Marchal, Franck...
RTAS
2006
IEEE
14 years 2 months ago
Switch Scheduling and Network Design for Real-Time Systems
The rapid need for high bandwidth and low latency communication in distributed real-time systems is driving system architects towards high-speed switches developed for high volume...
Sathish Gopalakrishnan, Marco Caccamo, Lui Sha
HICSS
2003
IEEE
151views Biometrics» more  HICSS 2003»
14 years 2 months ago
A Simple GSPN for Modeling Common Mode Failures in Critical Infrastructures
It is now apparent that our nation’s infrastructures and essential utilities have been optimized for reliability in benign operating environments. As such, they are susceptible ...
Axel W. Krings, Paul W. Oman