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ASPDAC
2005
ACM
93views Hardware» more  ASPDAC 2005»
13 years 10 months ago
Power minimization for dynamic PLAs
—Dynamic programmable logic arrays (PLAs) which are built of the NOR–NOR structure, have been very popular in high performance design because of their high-speed and predictabl...
Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, ...
INFOCOM
2006
IEEE
14 years 2 months ago
Scheduling in Non-Blocking Buffered Three-Stage Switching Fabrics
— Three-stage non-blocking switching fabrics are the next step in scaling current crossbar switches to many hundreds or few thousands of ports. Congestion (output contention) man...
Nikolaos Chrysos, Manolis Katevenis
ITNG
2007
IEEE
14 years 2 months ago
Multi-path Routing for Mesh/Torus-Based NoCs
In networks-on-chip (NoC) designs, delay variations and crosstalk noise have become a serious issue with the continuously shrinking geometry of semiconductor devices and the incre...
Yaoting Jiao, Yulu Yang, Ming He, Mei Yang, Yingta...
DSD
2009
IEEE
118views Hardware» more  DSD 2009»
14 years 3 months ago
Internet-Router Buffered Crossbars Based on Networks on Chip
—The scalability and performance of the Internet depends critically on the performance of its packet switches. Current packet switches are based on single-hop crossbar fabrics, w...
Kees Goossens, Lotfi Mhamdi, Iria Varela Senin
ICC
2007
IEEE
14 years 2 months ago
LOOFA-PB: A Modified LOOFA Scheduler for Variable-Length Packet Switching
—The LOOFA algorithm is a cell-based scheduler for CIOQ crossbar switches that can guarantee the work-conserving property in a cell-based switch if the crossbar switch works twic...
Afshin Shiravi, Paul S. Min