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GLVLSI
2005
IEEE
132views VLSI» more  GLVLSI 2005»
14 years 2 months ago
FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
Abdallah Merhebi, Otmane Aït Mohamed
CF
2006
ACM
14 years 13 days ago
The potential of the cell processor for scientific computing
The slowing pace of commodity microprocessor performance improvements combined with ever-increasing chip power demands has become of utmost concern to computational scientists. As...
Samuel Williams, John Shalf, Leonid Oliker, Shoaib...
ISCA
2011
IEEE
269views Hardware» more  ISCA 2011»
13 years 12 days ago
Crafting a usable microkernel, processor, and I/O system with strict and provable information flow security
High assurance systems used in avionics, medical implants, and cryptographic devices often rely on a small trusted base of hardware and software to manage the rest of the system. ...
Mohit Tiwari, Jason Oberg, Xun Li 0001, Jonathan V...
HCI
2009
13 years 6 months ago
High-Fidelity Prototyping of Interactive Systems Can Be Formal Too
The design of safety critical systems calls for advanced software engineering models, methods and tools in order to meet the safety requirements that will avoid putting human life ...
Philippe A. Palanque, Jean-François Ladry, ...
EUROSYS
2006
ACM
14 years 5 months ago
Reducing TCB complexity for security-sensitive applications: three case studies
The large size and high complexity of securitysensitive applications and systems software is a primary cause for their poor testability and high vulnerability. One approach to all...
Lenin Singaravelu, Calton Pu, Hermann Härtig,...