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DAC
2005
ACM
14 years 9 months ago
Microarchitecture-aware floorplanning using a statistical design of experiments approach
Since across-chip interconnect delays can exceed a clock cycle in nanometer technologies, it has become essential in high performance designs to add flip-flops on wires with multi...
Vidyasagar Nookala, Ying Chen, David J. Lilja, Sac...
ISCA
2007
IEEE
162views Hardware» more  ISCA 2007»
14 years 3 months ago
BulkSC: bulk enforcement of sequential consistency
While Sequential Consistency (SC) is the most intuitive memory consistency model and the one most programmers likely assume, current multiprocessors do not support it. Instead, th...
Luis Ceze, James Tuck, Pablo Montesinos, Josep Tor...
JSSPP
2004
Springer
14 years 2 months ago
Reconfigurable Gang Scheduling Algorithm
 Using a single traditional gang scheduling algorithm cannot provide the best performance for all workloads and parallel architectures. A solution for this problem is the use of...
Luís Fabrício Wanderley Góes,...
DAC
2009
ACM
14 years 9 months ago
A DVS-based pipelined reconfigurable instruction memory
Energy consumption is of significant concern in battery operated embedded systems. In the processors of such systems, the instruction cache consumes a significant fraction of the ...
Zhiguo Ge, Tulika Mitra, Weng-Fai Wong
HICSS
2003
IEEE
154views Biometrics» more  HICSS 2003»
14 years 1 months ago
Project JXTA-C: Enabling a Web of Things
The Web, the collection of all devices connected to the Internet, is on the verge of experiencing a massive evolution from a Web of Computers to a Web of Things as new devices suc...
Bernard Traversat, Mohamed Abdelaziz, Dave Doolin,...