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ICPP
2007
IEEE
14 years 2 months ago
Loop-level Speculative Parallelism in Embedded Applications
As multi-core microprocessors are becoming widely adopted, the need to extract thread-level parallelism (TLP) from single-threaded applications in a seamless fashion increases. In...
Md. Mafijul Islam, Alexander Busck, Mikael Engbom,...
IPPS
2007
IEEE
14 years 2 months ago
SWARM: A Parallel Programming Framework for Multicore Processors
Due to fundamental physical limitations and power constraints, we are witnessing a radical change in commodity microprocessor architectures to multicore designs. Continued perform...
David A. Bader, Varun Kanade, Kamesh Madduri
CODES
2005
IEEE
14 years 2 months ago
System-level design automation tools for digital microfluidic biochips
Biochips based on digital microfluidics offer a powerful platform for massively parallel biochemical analysis such as clinical diagnosis and DNA sequencing. Current full-custom de...
Krishnendu Chakrabarty, Fei Su
ASPDAC
2005
ACM
140views Hardware» more  ASPDAC 2005»
14 years 2 months ago
A multi-level transmission line network approach for multi-giga hertz clock distribution
-In high performance systems, process variations and fluctuations of operating environments have significant impact on the clock skew. Recently, hybrid structures of H-tree and m...
Hongyu Chen, Chung-Kuan Cheng
AGENTS
2001
Springer
14 years 1 months ago
It knows what you're going to do: adding anticipation to a Quakebot
The complexity of AI characters in computer games is continually improving; however they still fall short of human players. In this paper we describe an AI bot for the game Quake ...
John E. Laird