118 search results - page 11 / 24 » A technique for minimizing power during FPGA placement |
ICCD
2004
IEEE
14 years 5 months ago
2004
IEEE
I/O placement has always been a concern in modern IC design. Due to flip-chip technology, I/O can be placed throughout the whole chip without long wires from the periphery of the...
DAC
2006
ACM
14 years 9 months ago
2006
ACM
Transistor leakage is poised to become the dominant source of power dissipation in digital systems, and reconfigurable devices are not immune to this problem. Modern FPGAs already...
MDM
2009
Springer
14 years 3 months ago
2009
Springer
— This work aims at minimize the cost of answering snapshot multi-predicate queries in high-communication-cost networks. High-communication-cost (HCC) networks is a family of net...
SLIP
2003
ACM
14 years 1 months ago
2003
ACM
In this paper, we describe an accurate metric (perimeter-degree) for measuring interconnection complexity and effective use of it for controlling congestion in a multilevel framew...
DAC
2007
ACM
14 years 9 months ago
2007
ACM
Thermal problems and limitations on interlayer via densities are important design constraints on three-dimensional integrated circuits (3D ICs), and need to be considered during g...