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» A technique for minimizing power during FPGA placement
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ICES
2005
Springer
177views Hardware» more  ICES 2005»
14 years 26 days ago
Evolving Hardware by Dynamically Reconfiguring Xilinx FPGAs
Evolvable Hardware arises as a promising solution for automatic digital synthesis of digital and analog circuits. During the last decade, a special interest has been focused on evo...
Andres Upegui, Eduardo Sanchez
SIGMOD
2009
ACM
250views Database» more  SIGMOD 2009»
14 years 7 months ago
Query processing techniques for solid state drives
Solid state drives perform random reads more than 100x faster than traditional magnetic hard disks, while offering comparable sequential read and write bandwidth. Because of their...
Dimitris Tsirogiannis, Stavros Harizopoulos, Mehul...
ICCAD
2006
IEEE
149views Hardware» more  ICCAD 2006»
14 years 1 months ago
Fast decap allocation based on algebraic multigrid
Decap (decoupling capacitor) is an effective technique for suppressing power supply noise. Nevertheless, over-usage of decap usually causes excessive power dissipation. Therefore...
Cheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen
ICASSP
2008
IEEE
14 years 1 months ago
Parameterized design framework for hardware implementation of particle filters
Particle filtering methods provide powerful techniques for solving non-linear state-estimation problems, and are applied to a variety of application areas in signal processing. Be...
Sankalita Saha, Neal K. Bambha, Shuvra S. Bhattach...
GLVLSI
2007
IEEE
189views VLSI» more  GLVLSI 2007»
14 years 1 months ago
Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems
The path-delay fault simulation of functional tests on complex circuits such as current processor-based systems is a daunting task. The amount of computing power and memory needed...
Paolo Bernardi, Michelangelo Grosso, Matteo Sonza ...