Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems

The path-delay fault simulation of functional tests on complex circuits such as current processor-based systems is a daunting task. The amount of computing power and memory needed for verifying or grading functional test programs capabilities employing traditional techniques is huge and constitutes a serious bottleneck in the test flow. In this paper we propose a new mechanism for grading functional test program path-delay coverage (1) relying on FPGAbased emulation, (2) based on suitable instrumentation of the circuit structure and (3) exploiting ad hoc modules to minimize the host performance requirements stemming from the experiment management. The proposed setup reduces the grading time by several orders of magnitude with respect to software environments. Moreover, the experimented mechanism is capable of pinpointing the clock cycles when path activation arises, thus providing a key for relating excitation conditions to the executed instructions. Categories and Subject Descriptors...

• Type: Conference
• Year: 2007
• Where: GLVLSI
• Authors: Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda
• Keywords: Functional Test, Functional Test Program, GLVLSI 2007, Path-delay Fault Simulation, VLSI