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HPCA
2009
IEEE
14 years 10 months ago
Voltage emergency prediction: Using signatures to reduce operating margins
Inductive noise forces microprocessor designers to sacrifice performance in order to ensure correct and reliable operation of their designs. The possibility of wide fluctuations i...
Vijay Janapa Reddi, Meeta Sharma Gupta, Glenn H. H...
JILP
2000
90views more  JILP 2000»
13 years 9 months ago
Speculative Updates of Local and Global Branch History: A Quantitative Analysis
In today's wide-issue processors, even small branch-misprediction rates introduce substantial performance penalties. Worse yet, inadequate branch prediction creates a bottlen...
Kevin Skadron, Margaret Martonosi, Douglas W. Clar...
LCTRTS
1999
Springer
14 years 2 months ago
Live Memory Analysis for Garbage Collection in Embedded Systems
Real-time garbage collection is essential if object-oriented languages (in particular, Java) are to become predictable enough for real-time embedded systems. Although techniques f...
Patrik Persson
IPPS
2007
IEEE
14 years 4 months ago
Power-Aware Speedup
Power-aware processors operate in various power modes to reduce energy consumption with a corresponding decrease in peak processor throughput. Recent work has shown power-aware cl...
Rong Ge, Kirk W. Cameron
ISLPED
2007
ACM
169views Hardware» more  ISLPED 2007»
13 years 11 months ago
Throughput of multi-core processors under thermal constraints
We analyze the effect of thermal constraints on the performance and power of multi-core processors. We propose system-level power and thermal models, and derive expressions for (a...
Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Ch...