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ICPP
2007
IEEE
14 years 2 months ago
RECN-IQ: A Cost-Effective Input-Queued Switch Architecture with Congestion Management
As the number of computing and storage nodes keeps increasing, the interconnection network is becoming a key element of many computing and communication systems, where the overall...
Gaspar Mora, Pedro Javier García, Jose Flic...
IPPS
2010
IEEE
13 years 5 months ago
Restructuring parallel loops to curb false sharing on multicore architectures
The memory hierarchy of most multicore systems contains one or more levels of cache that is shared among multiple cores. The shared-cache architecture presents many opportunities f...
Santosh Sarangkar, Apan Qasem
CISIS
2009
IEEE
14 years 2 months ago
Application of a Critical Chain Project Management Based Framework on Max-Plus Linear Systems
Abstract. We focus on discrete event systems with a structure of parallel processing, synchronization, and noconcurrency. We use max-plus algebra, which is an effective approach fo...
Hirotaka Takahashi, Hiroyuki Goto, Munenori Kasaha...
TCS
2008
13 years 7 months ago
Solving NP-complete problems in the tile assembly model
Formalized study of self-assembly has led to the definition of the tile assembly model, a highly distributed parallel model of computation that may be implemented using molecules ...
Yuriy Brun
SP
2010
IEEE
190views Security Privacy» more  SP 2010»
13 years 5 months ago
Noninterference through Secure Multi-execution
A program is defined to be noninterferent if its outputs cannot be influenced by inputs at a higher security level than their own. Various researchers have demonstrated how this pr...
Dominique Devriese, Frank Piessens