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ARCS
2009
Springer
14 years 3 months ago
Improving Memory Subsystem Performance Using ViVA: Virtual Vector Architecture
The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software c...
Joseph Gebis, Leonid Oliker, John Shalf, Samuel Wi...
SAMOS
2009
Springer
14 years 3 months ago
Multiple Description Scalable Coding for Video Transmission over Unreliable Networks
Developing real time multimedia applications for best effort networks such as the Internet requires prohibitions against jitter delay and frame loss. This problem is further compl...
Roya Choupani, Stephan Wong, Mehmet R. Tolun
RECONFIG
2008
IEEE
225views VLSI» more  RECONFIG 2008»
14 years 2 months ago
A Hardware Filesystem Implementation for High-Speed Secondary Storage
Platform FPGAs are capable of hosting entire Linuxbased systems including standard peripherals, integrated network interface cards and even disk controllers on a single chip. File...
Ashwin A. Mendon, Ron Sass
ACMACE
2006
ACM
14 years 2 months ago
Wireless home entertainment center: reducing last hop delays for real-time applications
Future digital entertainment services available to home users will share several characteristics: i) they will be deployed and delivered through the Internet, ii) a single media c...
Claudio E. Palazzi, Giovanni Pau, Marco Roccetti, ...
SIGCOMM
2004
ACM
14 years 1 months ago
Sizing router buffers
All Internet routers contain buffers to hold packets during times of congestion. Today, the size of the buffers is determined by the dynamics of TCP’s congestion control algor...
Guido Appenzeller, Isaac Keslassy, Nick McKeown